1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. In particular, the present invention relates to a semiconductor integrated circuit including a boost circuit for boosting a power supply voltage.
2. Description of the Related Art
A semiconductor integrated circuit has a built-in nonvolatile memory such as NAND flash memory capable of electrically achieving write and erase. In the semiconductor integrated circuit, an internal voltage generation circuit built in a chip generates the following various voltages with a single power supply. One is a high voltage required for write and erase operations. Another is a channel boost voltage for preventing a write error to a non-select memory cell. Another is a read voltage applied to a non-select memory cell in a read operation.
For example, the internal voltage generation circuit is composed of a boost circuit, a potential detection circuit, a clock generation circuit and a stabilization capacitor. Specifically, the boost circuit boosts a power supply voltage supplied externally. The potential detection circuit controls an output voltage of the boost circuit to a desired voltage (internal voltage). The clock generation circuit controls the operation of the boost circuit. The stabilization capacitor stores a boosted charge. The stabilization capacitor achieves a function as an instantaneous charge supply source for the following advantages. Namely, the ripple of the output of the boost circuit is prevented in a steady-state operation. In addition, when a large load is connected to an output terminal of the boost circuit, the output terminal is assisted so that the terminal does not fall below a certain voltage.
A NAND flash memory requires a high write voltage; for this reason, it has a built-in transistor having a high breakdown voltage insulating film thicker than a tunnel insulating film of a memory cell. The foregoing transistor having the thick insulating film is usable as a capacitor element. However, the insulating film is thick; for this reason, the capacitance per unit area is small. If a capacitor having a large capacitance is formed in a semiconductor integrated circuit, this is a factor of increasing a chip area.
The following technique has been disclosed as this kind of related art (see Japanese Patent No. 3173327). According to the foregoing technique, even if defect exists in a dielectric layer between electrodes having a boost voltage stabilization capacitance, the boost voltage stabilization capacitance is prevented from being destroyed.